Understanding the US need for Secure Microelectronics

The Department of Defense's (DoD) ability to provide superior capabilities to the American warfighter is dependent on its ability to incorporate rapidly evolving, cutting-edge and secure microelectronic devices into its defense systems such as Artificial Intelligence, quantum cryptology, and 5G.

DoD has made the shift from custom ASICs to commercial-microelectronics fabrication over the last few decades. In the past the US dominated the microelectronics system’s market and was able to “own” the supply chain. This is no longer the case, especially with China leading in AI and 5G, and Asian countries dominating commercial cutting-edge microelectronics manufacturing. This introduces security vulnerabilities to the US supply chain.

US companies produce all equipment necessary to manufacture microelectronic devices, except for the most important piece: the lithography machine. This machine „converts‟ the design of the device to physical patterns on the chip and determines the quality and capability of the device. The main supplier of this equipment is in The Netherlands: ASML, a $10bln company. ASML is focused on selling their equipment to the commercial microelectronics manufacturers for high-volume device manufacturing.

Separately a Direct Write (DW) electron-beam lithography (EBL) system has been developed in The Netherlands focusing on the unique microelectronics needs from the DoD (low-volume, high density, unique patterns, large devices, rapid prototyping, secure supply chain).
Combining high-volume device manufacturing (e.g. EUV lithography) with DW EBL creates mix- and-match strategies high-performance CMOS layers implemented using commercial semiconductor manufacturing steps. DW EBL will be used to do metal layer back-end processing.

EBL is the practice of streaming a focused beam(s) of electrons on a surface covered with an electron-sensitive film (resist) to etch desired shapes onto a substrate. This is accomplished primarily when electron beams react with resists, enabling selective removal of either the exposed or non-exposed regions. Electron microscopes converted for writing purposes have been in use since 1990, exhibiting line-width resolution capabilities now down to 3 and 7nm. State-of-the-art EB tools have line width resolution capabilities of 1.3nm @5Kev and 0.9 @20Kev (EB tools by JEOL).

ELB offers significant advantages in terms of quality control in IC manufacture with the smallest, cleanest patterns and shapes possible. Unfortunately, it is a very slow process and so has not yet transitioned from laboratory/R&D/prototyping use, mask or back end of the line wireline and via production in the microelectronics arena. Significant capital has been spent to improve throughput, and significant improvements have been demonstrated in node-sizes >28nm. However, the holy grail of cost-competitive advanced microelectronic production for EBL remains elusive. Some IC manufacturers (TSMC, Samsung) are claiming that they have achieved the manufacture of <10nm circuits on ICs using conventional optical (DUV) lithography and or extreme ultraviolet (EUV), but those assertions are being disputed as statistical permutations, not actual feature sizes based on gate length or half pitch width at metal layer 1 (M1).

Significant investment in multi-beam EBL has caught the eye of the USG (DTRA, AF/SMC, AFRL and Intelligence Community), private investors and microelectronic equipment manufacturers as node-sizes <10nm are extremely difficult to produce using conventional and advanced(immersion, DUV, etc.) lithographic means. Getting to smaller node sizes will enable further densification of circuitry on silicon and will yield ever more powerful and capable ICs.

E-Beam lithographic processes have been in use for decades, principally as mask writers and more recently as tool for Back End of Line (BEOL) via and wiring applications and are now emerging from niche microelectronics manufacturing to limited production. The United States Government (USG) has a need for custom high-performance, low-power, non-radiation and radiation-hardened Integrated Circuits (ICs), produced in a high mix and low volume at secure trusted facilities over extended program lifetimes. To meet USG requirements, trusted and assured production facilities need to provide a guaranteed source of progressively advanced IC lithography nodes. However, each new IC generation faces escalating lithography cost brought on by optical resolution limitations

Moreover, today’s optical lithography equipment (193nm technology, dry or immersion (193i)) is designed for high-volume manufacturing (tens of thousands of wafers starts per month) and is ill-suited for production of small quantities of a high mix ICs required by USG. It may very well be possible using these technologies to significantly enhance security by denying adversaries the ability to adulterate designs and/or to counterfeit, clone, or otherwise compromise ICs during fabrication.

The challenge ahead for EB/MEBL tool designers and manufacturers is to develop methods that can be easily ported to fabrication and packaging operations, especially advanced multichip modules like silicon interposers. EB mask and BEOL tools have demonstrated their utility and are incorporated in IC manufacturing. EB tool developers are still working to incorporate advanced tools into their process flow. There are considerable technology hurdles remaining and considerable investment required by leaders in the field of fabrication tools (e.g. Multi-Beam corporation, Advantest, and JEOL) before these tools will be market ready. Direct-write tools, on the other hand, already exist for BEOL wire lines and vias, and so can easily port to legacy lithography nodes IC fabrication, albeit only for very low-rate production. Investment in this arena is focused on enabling EB technology to fabricate 45 and 32nm ICs and achieve dramatically higher throughput of 10 wafers per hour. Here too, considerable technology hurdles and cost remain to be overcome

Use Cases

Secure Manufacturing

• Use of state-of-the-art foundries for front end wafer preparation for USG. There are two aspects here. The first one is with the MEBDW system installed at the trusted partner foundry. This brings the ability to the USG to directly write certain layers or features at the foundry - as there are no masks required - this can be executed under control of the USG.

• Use of state-of-the-art foundries where the front-end layers are finalized at the trusted commercial partner foundry and the back-end layers are finalized in a Trusted Foundry.

• Upgrading the 200mm (and smaller wafer sizes) Trusted Foundry infrastructure to more advanced technology nodes.

• Upgrading the III-V materials device manufacturing infrastructure. With the ability to handle different types of wafer materials -e.g. GaAs, InP, etc

• The absence of the need to use a mask as the features are written directly onto the wafers, eliminates the need to go to a third-party mask manufacturer - and takes a step with some security risks associated out of the process

Rapid Innovation
Cost Reduction